JieLi AC695N, AC696N Bluetooth Chip Hardware Design Specification - Circuit Design Guide (3)

1.4 DAC Anti-Interference Circuit Description

AC695N and AC696N support DACL/DACR differential mode and DACL/DACR/VCOMO stereo mode.

Schematic is as follows:

(1) It is recommended to reserve anti-interference circuits for the DAC section; if space is limited, only L4/L5/L6 can be reserved.

(2) For strict noise requirements, it is suggested to place AGND copper pour (or no pour) on both sides around the DAC circuit and solder points. Do not pour "digital GND" and keep away from "digital GND" to effectively eliminate high-frequency noise.

(3) L4/L5 should be fixed at 100nH or 120nH to effectively remove high-frequency TDD noise generated when a mobile phone is near the device during Bluetooth calls; L6 should be fixed at 220nH or 330nH to effectively remove high-frequency noise during music playback (try this method if LAYOUT is not optimal). Note: The reserved noise handling circuit on the DAC side increases cost. If the design is reasonable enough and noise requirements are not high, it can be omitted.

1.5 MIC Circuit Description

AC695N and AC696N support both analog silicon MIC and electret MIC.

Schematic is as follows:

Note:

For electret MIC solutions, AC695N requires a DC blocking capacitor on the MIC input. Pay attention to the difference from AC696N during design.

1.6 ESD Circuit Description

① Traces for analog sections like DACL, DACR, and related components are susceptible to ESD interference. Provide protection (e.g., increase spacing to GND, avoid GND pour under components).

② At the decoupling capacitor C1 for the DACVDD power supply, it is recommended to reserve a C2: 105 capacitor nearby to connect AGND and GND (can be omitted if design is reasonable).

Schematic is as follows: