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JL JieLi AC696N Series Chip Development – Timer Detailed Explanation: Differences and Selection Between sys_timer and usr_timer

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  Introduction Timers seem simple, but using them in the wrong place either increases power consumption or causes timing inaccuracies—and debugging can be quite troublesome. The JL JieLi AC696N SDK provides two sets of timers: sys_timer and usr_timer. When first getting started, it's easy to get confused—when to use which? Why does my timer become inaccurate after entering sleep? Can I perform work in the callback? I encountered all these issues while debugging low-power solutions on the AC696N development board. Here's a summary of the differences and selection logic, so you can directly reference it when writing code. Chip Product Introduction I. System Timer (sys_timer) – "Software Timer" Features: Managed by the systimer thread, synchronous interface. The callback executes in the same thread where the timer was added. Low Power: System can sleep; the timer will wake the system when it expires, without losing ticks. Use Case: Suitable for general tasks that ...
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JL JieLi AC696N Development Board – Advanced Power Management: Core Voltage Adjustment and Long-Press Reset

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Introduction Previously, we discussed reset source querying and I/O wake-up configuration—these are the basics of low power. However, in real products, there are a few more power management pitfalls worth addressing separately: when to raise the core voltage, how to control the SD card power pin, and how to configure long-press reset to avoid false triggers. These settings may seem minor, but if done incorrectly, they can cause mysterious problems—like intermittent crashes when running high-frequency applications, or long-press reset that's either too sensitive or too sluggish, hurting the user experience. Recently, while debugging a product with SD card playback on the AC696N development board, I went through these configurations and organized them here for future reuse. I. When Do You Need to Raise the Core Voltage? When the chip runs at higher frequencies or under heavy load, you may need to increase the core voltage (SYSVDD) to ensure stability. How to do it: In clock_manager...
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